{"type":"video","version":"1.0","html":"<iframe width=\"560\" height=\"315\" sandbox=\"allow-same-origin allow-scripts allow-popups allow-forms\" title=\"UNIT-5,    12. Behavioural Modeling in Verilog\" src=\"https://visualhub.fxcams.in/videos/embed/e01ad668-e2df-4cda-803f-3606c5f555a4\" frameborder=\"0\" allowfullscreen></iframe>","width":560,"height":315,"title":"UNIT-5,    12. Behavioural Modeling in Verilog","author_name":"21EC6601- VLSI DESIGN","author_url":"https://visualhub.fxcams.in/video-channels/21ec6601_vlsidesign","provider_name":"PeerTube","provider_url":"https://visualhub.fxcams.in","thumbnail_url":"https://visualhub.fxcams.in/lazy-static/previews/03e0442e-3d98-48c0-bee4-2c4aa893d0c8.jpg","thumbnail_width":850,"thumbnail_height":480}