{"type":"video","version":"1.0","html":"<iframe width=\"560\" height=\"315\" sandbox=\"allow-same-origin allow-scripts allow-popups allow-forms\" title=\"UNIT-5,      11. Dataflow Modeling in Verilog\" src=\"https://visualhub.fxcams.in/videos/embed/6add3bb1-4993-407f-9fdc-59d6ca11e113\" frameborder=\"0\" allowfullscreen></iframe>","width":560,"height":315,"title":"UNIT-5,      11. Dataflow Modeling in Verilog","author_name":"21EC6601- VLSI DESIGN","author_url":"https://visualhub.fxcams.in/video-channels/21ec6601_vlsidesign","provider_name":"PeerTube","provider_url":"https://visualhub.fxcams.in","thumbnail_url":"https://visualhub.fxcams.in/lazy-static/previews/cdf929d0-83a3-4135-ae55-17b5fdc80bd1.jpg","thumbnail_width":850,"thumbnail_height":480}